Multi-FPGA Emulation Platform：4 Altera Stratix 3 SL340
Full differential interconnect, up to 200MHz
DDR2 SODIMM slots for every FPGA
Automatic Thermal / Voltage Supervision
Built-in JTAG interconnect test
Schem-to-gerber with optimized BOM: 16 man-weeks
top schematic:
Freescale MPC5121 SoC System
Dual processor, DDR-2, USB 2.0
10 Layers
Schem-to-gerber with BOM optimization 8 man-weeks
PCB layout (a CAD layout view):
PCB layout (a CAD routing layer view):
Altera FPGA PCI System
DDR, High speed
18 Layers
Schem-to-gerber with BOM optimization 6 man-weeks
PCB layout (a CAD layout view):
PCB layout (a CAD routing layer view):
